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an214 74f extended octal-plus family applications june 1988 (revised june 1996) integrated circuits
philips semiconductors application note an214 74f extended octal-plus family applications 2 june 1988 revised: june 1996 74f extended octal-plus family features ? 8-, 9-, and 10-bit alight-loado bus products buffers/drivers with and without latches or registers with and without 8-bit parity checker/generator transceivers with and without dual registers with and without 8-bit parity checker/generator ? patented alight-loado inputs: input current = 20 m a per input transceiver i/o pins = 70 m a ? high performance output drive currents: i ol = 64ma/48ma @ 5%/10% v cc i oh = 15ma/3ma @ 5%/10% v cc ? aflow-througho or abroadsideo i/o pin configuration ? ideal for mos cpu, peripherals and semi-custom bus interface ? 24-pin, 300mil-wide, plastic slim-dips ? high performance buffers e t p(max) = 7.5ns ? high performance latches/registers e f t = 100mhz introduction the 74f extended octal-plus family incorporates all of the latest philips semiconductors octal, 9-bit and 10-bit buffer, transceiver, latch and register functions. all devices in this family utilize the philips semiconductors patented alight-loado npn, 20 m a input current structure and have aflow-througho or abroadsideo input/output pin configurations where the inputs and outputs are lined-up on opposite sides of a standard 24-pin slim-dip package. the alight-loado inputs, abroadsideo design and high functional density/performance of the family make this product line ideal for buffering the limited drive capabilities of standard, custom and semicustom mos vlsi devices to the rigorous environments of today's leading edge high performance logic designs. the family also is an excellent choice for all general interface applications. aflow-througho design the aflow-througho or abroadsideo chip layout/package design is illustrated in figure 1 showing the block diagrams and pin configurations of the 74f828 10-bit inverting buffer. note that all of these abroadsideo designs allow logic signals to flow into one side and out of the other without crossing or folding back on signal paths such as the 74f240 octal buffers (figure 2). if you compare the physical layout requirements of the path of pc board bus lines for the 74f828 to that of the 74f240's azig-zago path, you will see the significant advantages of the 74f extended octal-plus family's aflow-througho design in simplifying the design and layout of large, high density, bus-oriented pc boards. the 24-pin, 300mil-wide, slip-dip solution with the advent of advanced schottky ttl technology came the ability to significantly increase the functional density of standard logic building blocks. however, not until the development of the 24-pin, 300mil-wide, slim-dip package was it possible to take full advantage of these new chip densities. the entire family provides significant advantages in package count, pin count and packing density when compared to older technologies. further density enhancements can be achieved by using philips surface mounted packages. by combining high functional density into a 24-pin 300mil-wide slim-dip package, the philips semiconductors 74f extended octal-plus family allows the reduction of pc board parts count and cost while optimizing layout with abroadsideo chip designs, reducing total system power dissipation and increasing system reliability. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 oe 0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 v cc o 0 o 1 o 2 o 3 o 4 o 5 o 7 o 6 o 8 o 9 oe 1 gnd sf01329 figure 1. 74f828 broadside pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 oe a ia0 yb 0 ia1 yb 1 ia2 yb 2 ia3 yb 3 gnd v cc oe b ya 0 ib0 ya 1 ib1 ya 2 ya 3 ib2 ib3 sf01330 figure 2. 74f240 'zig-zago pin configuration
philips semiconductors application note an214 74f extended octal-plus family applications june 1988 3 sf01331 d5 d6 r1 6k d4 q1 q1a q2 y in d3 v cc r6 6k r5 5k r4 50 q5 r2 50 r3 10k q3 q4 d2 d1 q6 r8 2k q7 r7 7.5k d7 q8 r9 2.8k q9 q10 d8 d9 en r10 2.8k r11 2.8k q12 d10 r12 500 r13 10k d11 q11 q13 r14 d13 d12 y out i ol options: 1) if i oh /i ol = 15/64 ma r14 = 12 w r11 = 2.8k w r10 = 2.8k w r12 = 500 w 2) if i oh /i ol = 3/24 ma r14 = 30 w r11 = 5k w r10 = 5k w r12 = 2k w figure 3. 74f455 buffer/drive cell circuit diagram the 8-, 9-, and 10-bit series 24-pin solution whether your system requires an 8, 9-, or 10-bit bus interface, the extended octal-plus family has standardized solutions in 24-pin/slim-dip/broadside input/output packages with corner power supply pins (12 & 24) and standard designations for common control functions located at or near the package corners. octals offer more mode control inputs than do the 9- or 10-bit products. virtually all family devices with 3-state outputs are guaranteed to source/sink 15/64ma @ v oh /v ol = 2.0/0.55v (except for the 74f841846 latched drivers, which are spec'ed at 15ma/48ma). the a n port outputs of several of the family's transceivers are guaranteed to supply 3ma/48ma). the octal parity bus series offers several notable exceptions to the above standard pinouts. this series has three parts with two center-package ground pins to minimize ground-bounce noise. all outputs (except the a n port of the 74f657 parity bus transceiver spec'ed at 3ma/24ma) are guaranteed to source/sink more than 15ma/64ma. current pc board, multi-layer technology make is possible to take into consideration the physical location of input/output pins, transmission line characteristics and supply power distribution. lining up all inputs and output on opposite sides of the package allows the address, data and control bus signal to flow in a direct physical path from the m p cpu through the bus interface chips and onto the appropriate bus. this abroadsideo bus design approach produces very clean pc board layouts and may, in fact eliminate and entire pc board interconnection layer. standardization of power supply, mode control and input/output pins, whether 8-, 9-, or 10-bit bus functions, permits simplified, structured pc board layout. input structures referring to figure 3, the 74f455 inverting buffer/driver cell circuit diagram is an example of the family's input and output circuitry. the patented philips semiconductors alight-loado npn input structure (q1/23/4/5, r1/2/3/4/5/6 and d4) and turn-off speed-up circuit (q2 and d2/3) are used throughout the 74f extended octal-plus family. the alight-loado npn input is actually a high speed, differential amplifier with the reference side, the anode of d4, clamped at two diode voltage drops above ground (be junctions of q8/9/10 and q 11 of 1.4v at 25 c). when the v ih rises above this clamp voltage, the be junction of q1 is forward based allowing beta amplified, ce current to flow into the <1.0ma constant current source, q3 (driven by q4/5 and r2/3/4/5/6). the beta of q1 is guaranteed, by design, to be >50, thereby guaranteeing that the input base bias current will be <20 m a. the emitter of q1 rises to 1v be ( 300mv) below the v ih , reverse biasing d4 and permitting c8/9/10 base bias current to flow through r1. the patented turn-off circuit consisting of q2 and d2/3 produces a dynamic speed to help turn q8/9/10 off quickly. during the time that the q1 is turned-on (input = v ih >2.0v), the revers-biased schottky diode, d2, acting as a capacitor, will be charged to the voltage at the emitter of q1a or 1v be voltage drop below the input (>2.0 1v be ). when the input is switched to philips semiconductors application note an214 74f extended octal-plus family applications june 1988 4 transceivers have an input loading current of 70 m a, which is the combination of the alight-loado npn input structure's 20 m a and the 3-state hi-z output's 50 m a leakage current. the low alight-loado input current and high speed performance makes this family ideal for interfacing to low drive capability, slower mos cpu, peripherals and semi-custom chips used in most of today's state-of-the-art logic designs. besides very low input current requirements, this alight-loado input has another significant advantage over atraditionalo input structures: very low input capacitance (smaller stored charge) due to very small device geometries. therefore, when extended octal-plus devices are connected to a bus, they present less ac bus loading and do not significantly lower the characteristic impedance of the bus to the extent atraditionalo input structures do. thus, the amount of the ac current a bus driver has to produce to change the state of the bus is lowered and in many cases can make a difference between incident wave switching of the bus versus losing time waiting for a reflected wave. the philips semiconductors 74f alight-loado input structure is discussed in more detail in application note an215 . output drive capabilities virtually all devices in the extended octal-plus family are guaranteed to source/sink more than 15ma/64ma @ v oh v ol = 2.0/0.55v. one exception is the 74f841-thru-846 series of bus interface latches which are specified at 15/48ma. several of the family's transceiver products have lower a n output drive capabilities to reduce package power dissipation. refer to tables 1 and 3. for example, the 74f657 parity bus transceiver has two output ports with different capacities: the a n port is guaranteed to source/sink 3ma/24ma (i oh /i ol = 2.4/0.50v), and the b n port has an output drive capability of 15ma/64ma at 2.0v/0.55v. the 74f657's a n port is designed to interface the chip side of the pc board to the backplane bus, while the b n port is capable of driving a transmission line or bus backplane line. referring to figure 3, all of the family's 3-state, totem-pole output structures have a schottky blocking diode, d13, in their pull-up output structures. these diodes block leakage current from flowing into the outputs when v cc is either open or shorted to ground. this gives a very important advantage of being able to power down a pcb (or several pcbs) without disabling the bus and even without producing any glitching on the bus due to an undesired change in the output state of the device being powered down. the output short-circuit (i os ) limiting resistor (r14), the anode-to-cathode resistance/voltage drop of d13 and the collector-to-emitter/base-to-emitter resistance/voltage drop of q13 limit the amount of current that can be sourced from a high level output at a specified v oh . for most of the parts in the family, r14 is equal to 12 w . the a n port of several of the transceivers utilize an r14 of 30 w producing i oh (@ v oh = 20v) of 6ma versus 15ma from the b n ports 12 w r14. the output high level sourcing current, i oh , at a specified output voltage, v oh , can be calculated by subtracting the voltage drops of d13, the pull-up darlington transistor, q12/13, and the desired v oh level from v cc and dividing by the value of r14 plus the anode-to-cathode resistance of d13 and the collector-to-emitter/ base-to-emitter resistance. assumptions: v d13 0.5v @ r on = 3 w @ 25 c), v q12/13 1.2v @ r on = 8 w @ 25 c) i oh = 1[v cc (v d13 + v q12/q13 + v oh )]/(r14 + r d13 + r q13 ). i oh (r14 = 12 w ) = [4.5v(0.5v + 1.2v + 2.0v)]/23 w = 35ma i oh (r14 = 30 w ) = [4.5v(0.5v + 1.2v + 2.0v)]/41 w = 20ma i os = i oh @ v oh = 0.0v and v cc = 5.5v i os (r14 = 12 w ) = [5.5v(0.5v + 1.2v)]/23 w = 165ma i os (r14 = 30 w ) = [5.5v(0.5v + 1.2v)]/41 w = 93ma obviously, we have been very conservative in the i oh specification to guardband against all conditions of temperature and input/output/supply voltage levels. the r on resistances of the output pullup transistors and blocking diode are large enough to prevent i os from exceeding 225ma for r14 = 12 w and 150ma for r14 = 30 w . (refer to table 1.) table 1. family output drive capabilities using the 74f657 parity bus transceiver dc electrical characteristics over recommended operating conditions, v il = max and v ih = min) symbol parameter test conditions min typ max unit all out p uts i oh = 3ma 10% v cc 2.4 v v o high level out p ut voltage all o u tp u ts i oh = 3ma 5% v cc 2.7 3.4 v v oh high - le v el o u tp u t v oltage b p ort parity error i oh = 15ma 10% v cc 2.0 v b n port , parity , error i oh = 15ma 5% v cc 2.0 v a p ort i ol = 24ma 10% v cc 0.35 0.50 v v o low level out p ut voltage a n port i ol = 24ma 5% v cc 0.35 0.50 v v ol lo w- le v el o u tp u t v oltage b p ort parity error i ol = 48ma 10% v cc 0.40 0.55 v b n port , parity , error i ol = 48ma 5% v cc 0.40 0.55 v i os a n output high level short circuit current (r14 = 30 w ) v cc = max 150 ma i os b n output high level short circuit current (r14 = 12 w ) v cc = max 225 ma
philips semiconductors application note an214 74f extended octal-plus family applications june 1988 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 d c q r d c q r d c q r d c q r d c q r d c q r d c q r d c q r oe0 oe1 d0 d1 d2 d3 d4 d5 d6 d7 mr gnd f845/6 oe d0 d1 d2 d3 d4 d5 d6 d7 d8 mr gnd f843/4 oe d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 gnd f841/2 v cc o0/o0 o1/o1 o2/o2 o3/o3 o4/o4 o5/o(5 o6/o6 o7/o7 o8/o8 o9/o9 cp/le f841/2 v cc o0/o0 o1/o1 o2/o2 o3/o3 o4/o4 o5/o5 o6/o6 o7/o7 o8/o8 en cp/le f843/4 v cc oe2 o0/o0 o1/o1 o2/o2 o3/o3 o4/o4 o5/o5 o6/o6 o7/o7 en cp/le f845/6 sf01332 f825/6 f823/4 f821/2 f821/2 f823/4 f825/6 cp 8216 le 8416 figure 4. 74f82x and 74f84x registered/latched buffer pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 oeba0 a0 a1 a2 a3 a4 a5 a6 a7 a8 oeba1 gnd 9-bit oeba a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 gnd 10-bit oe0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 gnd 10-bit v cc o0/o0 o1/o1 o2/o2 o3/o3 o4/o4 o5/o(5 o6/o6 o7/o7 o8/o8 o9/o9 cp/le v cc b0/b0 b1/b1 b2/b2 b3/b3 b4/b4 b5/b5 b6/b6 b7/b7 b8/b8 b9/b9 cp/le v cc b0/b0 b1/b1 b2/b2 b3/b3 b4/b4 b5/b5 b6/b6 b7/b7 b8/b8 oeab0 oeab1 sf01333 xcvrs xcvrs buffers f863/4 f861/2 f827/8 9-bit xcvrs f863/4 10-bit xcvrs f861/2 10-bit buffers f827/8 figure 5. 74f827/8 and 74f8614 buffers and transceivers pin configurations
philips semiconductors application note an214 74f extended octal-plus family applications june 1988 6 a0 oe b0 d c d c dir cpba sba cpab sab i of 8 channels to 7 other channels 74f646a649a (74f646a shown) 21 2 4 20 3 23 22 1 a0 oeba b0 d c d c i of 8 channels to 7 other channels 74f651a654a (74f651a shown) 21 3 23 22 1 2 4 20 oeab cpba sba cpab sab sf01334 figure 6. 74f646a649a and 74f651a654a registered transceivers simplified logic block diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 oeba0 sab oeab a0 a1 a2 a3 a4 a5 a6 a7 gnd oeba sab oeab a0 gnd cpab sab dir a0 a1 a2 a3 a4 a5 a6 a7 gnd v cc cpba sba oe b0 b1 b2 b3 b4 b5 b6 b7 v cc cpba sba oeba b0 b1 b2 b3 b4 b5 b6 b7 v cc cpba sba oeba b0 b1 b2 b3 b4 b5 b6 b7 3-st/oc f648a/9a see block diagram cpab sab dir a0 a1 a2 a3 a4 a5 a6 a7 gnd 3-st/oc f646a/7a v cc cpba sba oe b0 b1 b2 b3 b4 b5 b6 b7 3-st/oc f651a/3a 3-st/oc f652a/4a 3-st/oc f652a/4a 3-st/oc f651a/3a 3-st/oc f648a/9a 3-st/oc f646a/7a a1 a2 a3 a4 a5 a6 a7 sf01335 figure 7. 74f646a649a and 74f651a654a dual registered transceivers pin configurations
philips semiconductors application note an214 74f extended octal-plus family applications june 1988 7 real time bus transfer bus b to bus a real time bus transfer bus a to bus b storage from a, b, or a and b transfer stored data to a and/or b oeab oeba cpab cpba sab sba oeab oeba cpab cpba sab sba oeab oeba cpab cpba sab sba oeab oeba cpab cpba sab sba bus a bus a bus a bus a bus b bus b bus b bus b sf00409 l lx xxl hh xxlx x h xxx lxx xx lh xx h l h or l h or l h h figure 8. 74f651a654a registered transceivers storage options (74f646a649a not shown) table 2. parity bus family versus the competition part number description total # of pins t pdmax * in to out t pdmax * in to parity i ccmax ** power pins broadside design 74f455/f456 vs octal parity buffer 24 7.5ns 16.0ns 110ma center yes vs . 74f240/f244 + 74f280 octal parit y b u ffer 38 7.5ns 14.5ns 125ma corner no 74f655a/f656a vs octal parity buffer 24 7.5ns 16.0ns 110ma corner yes vs . 74f240/f244 + 74f280 octal parit y b u ffer 38 7.5ns 14.5ns 125ma corner no 74f657 vs. octal parity transceiver 24 7.5ns 16.0ns 110ma center yes 74f240/f245 + 74f280 + 1 and gate octal parit y transcei v er 38 8.0ns 14.5ns 125ma corner no notes: * propagation delays of data in-to-data out and in-to-parity out, t amb = 0 c to 70 c, v cc = +5.0v 10%, output load = c l = 50pf, and r l = 500 w . ** worst case power, t amb = 0 c to 70 c, v cc = +5.0v 10%, output load = c l = 50pf, and r l = 500 w . 74f82174f863 series the 74f821 through 74f863 series of octal 9-bit and 10-bit buffers, latch buffers, register buffers and transceivers are standardized around the amd 298xx series with one significant differenceethe philips semiconductors alight-loado npn input offers a 50:1 reduction in input loading (1000 m a vs. 20 m a). this series illustrates the standardized on 24-pin/300mil-wide slim-dip packages, abroadsideo input/output pinouts and control function pins. all 74f8xx 3-state outputs are guaranteed to source/sink 15ma/64ma, except for the 74f84x latched buffers, which are specified at 15ma/48ma. the logic diagram and pin configurations of the 74f828 non-inverting 10-bit buffer (figure 1) and the 74f821826 and 74f841846 registered/latched buffers (figure 4) are excellent illustrations of the standardized pin configuration illustrating abroadsideo chip design. figure 5 shows the pinouts of the 74f827/828 buffers and 74f861864 transceivers. there currently are no 9-bit buffer offerings in this series. registered transceiver series the 74f646a649a and 74f651a654a octal dual-registered transceivers offer a alight-loado combination of a 74f245 type transceiver with two 74f373/374 type octal registers within a 24-pin slim-dip broadside input/output package. this series offers a significant 6:1 package count reduction advantage over older technologies. figure 6 shows the 74f646a and 74f651a transceivers simplified block diagrams, and this series' pin configurations are depicted in figure 7. figure 8 graphically illustrates four optional storage and transfer modes of the 74f651a octal, non-inverting, 3-state, dual-registered transceiver. the 74f654a will be used to explain the operation of the entire series. the 74f646a/648a (3-state, inv/ninv) and the 74f647/649 (o.c., inv/ninv) octal dual-registered transceivers offer optional signal direction control logic and output enable to the 74f651a654a series. this series allows you to store or real-time transfer data in either direction through the transceiver function. data at the a n port can be stored in either the a n port register or the b n register and, then, can
philips semiconductors application note an214 74f extended octal-plus family applications june 1988 8 be transferred either from the a n port register to the b n port outputs or from the b n port register to the a n port outputs. the same capabilities are available to data presented to the bport. when a port's output buffers are enabled (oe = low and dir = low for a n outputs enabled or high for b n outputs enabled), the sxx select inputs (sab and sba) control the two ex-or gates allowing the output port data to come either directly from the other port (real-time transfer) or from the other port's input storage register. the cpabn and cpba inputs are the low-to-high edge-triggered clock inputs for the a n port register and b n port register. data presented to either port's inputs can be clocked into its input register on a low-to-high cpxx input regardless of the logic levels on any of the other mode control inputs. the 74f651a654a's oeab and oeba output enable inputs may be tied together to enable the b outputs when high or a n outputs when held low or can be used separately to independently control the two output ports. tying the 74f651a654a's oeab and oeba together is logically equivalent to the dir input of the 74f646a649a. parity bus series advantages the increased functional density of the parity bus series produces a 2:1 package reduction (plus 1 and gate) and, therefore, 38:24 pin reduction. power dissipation savings of 82.5mw for the 74f455/456/655a/656a drivers and 137.5mw for the 74f657 are also achieved through shared internal logic. table 2 shows the package/pin advantage as well as the worst case propagation delays and i cc of the family versus their competition. figure 9 is a summary of the pin configurations of the entire parity bus drivers and transceiver series. the 74f455/456/655a/656a octal parity bus drivers and the 74f657 octal parity bus transceiver series combines the popular philips semiconductors 74f24x buffer/transceiver functions with the 74f280b 9-bit parity generator/checker, abroadsideo input/output pin configurations, alight-loado inputs and an increased guaranteed sink/source capabilities of 15ma/64ma for low impedance bus environments. the 74f445/446 drivers with their multiple center-package ground supply pins are logically identical to the 74f655a/656a drivers, except for the latter's single corner-package supply pins and an additional output enable input. the 74f657 parity bus transceiver allows the parity to be generated and checked in both directions in a single package replacing one 74f245 transceiver, 20-pin dip and two 74f280, 16-pin dips plus a couple of gates. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 oe1 oe2 pi i0 i1 i2 v cc i3 i4 i5 i6 i7 oe1 oe3 pi i0 gnd t/r a0 a1 a2 a3 a4 v cc a5 a6 a7 o/e error oe b0 b1 b2 b3 gnd gnd b4 b5 b6 b7 parity v cc oe2 y0 /y0 y1 /y1 y2 /y2 y3 /y3 y4 /y4 y5 /y5 y6 /y6 y7 /y7 s o s e xcvr f657 see block diagram buffer f655/6a buffer f455/6 buffer f455/6 buffer f655/6a xcvr f657 i1 i2 i3 i4 i5 i6 i7 s o s e y0 /y0 y1 /y1 y2 /y2 gnd gnd y3 /y3 y4 /y4 y5 /y5 y6 /y6 y7 /y7 sf01336 figure 9. 74f octal parity drivers/transceiver pin configurations
philips semiconductors application note an214 74f extended octal-plus family applications june 1988 9 74f657 operation the 74f657 parity bus transceiver, as shown in its simplified logic diagram, figure 10, is a combination of a 74f245 octal transceiver and a 74f280b 9-bit parity generator/checker plus one and gate. figure 11 expands the logic block diagram of the family's parity tree logic (inside the dashed line of figure 10). during transmit mode (a n = hi-z), the parity and error outputs are generated from the a n input/output port. in the receive mode, the b n port is the input from the system or mother board bus (b-port outputs = hi-z). for best speed performance, parity should always be generated from the a n port for the b n port (transmit mode), and parity error should always be checked for data coming in on the b-port (receive mode). even or odd parity generation and checking is determined by the even/odd input (even = high, and odd = low). in the transmit mode (t/r = high), transmitted data travels from the a-port to the b-port in less than 8.0ns generating a parity bit output in less than 16.0ns. whereas, in the receive mode (t/r = low), received data traverses from the b-port to the a-port path in, again, less than 8.0ns, but then the error checking output, being generated from the output data presented to the a-port and the parity input, takes an additional 16.5ns or less to stabilize. therefore, the total received-data-to-error checking output propagation time is the sum of the b n -to-a n delay (8ns) and the a n /parity-to-error output delay (16.5ns) or 22.5ns. however, in many cases, the propagation delay that has to be taken into consideration does not have to include parity calculation time and could be equal to that of just the transceiver part (8ns). this is due to the fact that it may not be too late to interrupt whatever needs to be interrupted in case of a parity error after the data has already gone by (i.e., via late bus error). parity tree analysis the basic 3-input comparator cell, inside the dashed line in figure 11, is used throughout the parity bus series. if there are an even number of high inputs (0 or 2) the output of the 3-input comparator cell will be high, while an odd number (1 or 3) will produce an output low. the 74f657's parity tree logic, combines four of the 3-input comparators with a 2-input comparator, a 2-input and gate and output buffers for parity and error to produce the complete parity generator/checker logic. eo a n a0a7) error re te parity 8l b n (b0b7) t/r 8l 8x 8l sf01337 figure 10. 74f657 simplified block diagram the 74f588 ieee-488 octal transceiver the 74f588 is a non-inverting ieee-488 standard transceiver contains eight bidirectional 3-state buffers. the b n port outputs can source/sink 15ma/64ma (guaranteed) and have series termination resistors as specified in the ieee-488 specification. the a n port, which interfaces to the pc board or system logic bus, is guaranteed to source/sink 3ma/24ma. the 74f588 pinout is identical to that of the 74f545 octal transceiver with the ieee-488 termination resistors in series with the b n port.
philips semiconductors application note an214 74f extended octal-plus family applications june 1988 10 a0 a1 a2 a3 a4 a5 a6 a7 re o/e error parity te re sf01338 figure 11. 74f657 parity tree logic diagram
philips semiconductors application note an214 74f extended octal-plus family applications june 1988 11 metastability in latches and registers interfacing a basically asynchronous real-world with synchronous logic systems can and does cause many circuit designer headaches. the problem: latches and registers which are normally considered to have only two stable states (high and low) actually have a thirdethe metastable state. this third operating point occurs when the corss-coupled latch is exactly balanced. this state is only stable when there is no noise on the chip which would tend to destabilize the perfect energy balance between the bi-stable states of the latch. refer to figure 12. metastability can occur when input data violate the setup time or hold time specifications at the clocking or strobing edge of the synchronizing clock input. with no system noise, the latch cannot decide ayes or noo, so it is possible for the latch to ago metastableo or amaybeo. with noise on the chip, random energy will anudgeo the latch toward one of its abi-stableo statesehigh or low. this metastable state time can range from nanoseconds to milliseconds. with today's very high performance logic families, the metastable condition can last for, perhaps, 1000 times the latch's normal propagation delay time. a metastable latch has an unpredictable delay time during which the output is between logic levels. this metastable state can easily last more than 50ns with today's high performance logic families and will cause systems to acrasho if great care is not taken with asynchronous, real-world interfacing. the d-type latch shown in figure 12 has data applied to nand gate 1 and data applied to nand gate 2. when the le (latch enable) input is low, gates 1 and 2 outputs are high and the g3/4 r-s latch is latched and stable. when le is high, the latch appears to be transparent to the data inputeq equals data. on the high-to-low transition of le, the data logic level that meets the latch's setup and hold time is stored in the latch. if data changes during the setup time to hold time period, it is possible for both outputs of gates 1 and 2 to be in the input thresholds region of gates 3 and 4, respectively. under these conditions, the latch (gates 3 and 4) could be perfectly balanced in the metastable state. eventually, chip and system noise will cause the latch to be forced into a high/low stable state. the extended octal-puls family, while not entirely immune, has been made metastable resistant by using design techniques which force the latch toward a stable state much more quickly than older bus interface families. data le q q g1 g2 g3 g4 v og3 = v ig4 v th = 1.35v metastable point energy energy low high 5.0 4.0 3.0 2.0 1.0 0 0 0.5 1.0 1.5 2.0 2.5 v og3 = v ig4 v th = 1.35v v in e input voltage v out e output voltage sf01339 figure 12. metastability in latches and registers
philips semiconductors application note an214 74f extended octal-plus family applications june 1988 12 dual-registered transceiver applications figure 13 illustrates how the 74f646a-649a and 74f651a-654a can be used to either synchronize data transfer between two systems, or pipeline data. data is stored in a register, then, while retrieving more data, the first data is read. when the second is available, it can either be stored or read directly. two slower systems can be multiplexed into a high speed system in the same way. parity bus transceiver applications figure 14 illustrates the functional density advantages of the parity bus series using the 74f657 in a typical microprocessor/data bus transceiver application. note the 74f245 + 74f280b version would still require a 2-input and gate and 3-state buffers for the parity and error outputs. and, of course, it would require an order of magnitude higher input current than a single 74f657 would, and would also introduce much higher capacitive loading (for both the bus and the microcontroller). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 74f652a/654a dual-register xcvr b7 b6 b5 b4 b3 b2 b1 b0 oeba sba cpba v cc cpab sab oeab a0 a1 a2 a3 a4 a5 a6 a7 gnd system 1 system 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 74f652a/654a dual-register xcvr system 1 8l 8l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 74f652a/654a dual-register xcvr 8l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 74f652a/654a dual-register xcvr 8l 8l 8l system 3 system 2 sf01340 figure 13. 74f extended octal-plus dual-registered transceiver applications 74f280b 9-bit comparator mos microprocessor/controller odd/even 74f245 octal transceiver t/r b0 b1 b2 b3 b4 b5 b6 b7 parity or error or 74f657 parity bus transceiver t/r b0 b1 b2 b3 b4 b5 b6 b7 parity mos microprocessor/controller error odd/even sf01341 figure 14. 74f657 parity bus transceiver applications
philips semiconductors application note an214 74f extended octal-plus family applications june 1988 13 table 3. the extended octal-plus family capabilities summary part number # bits polarity output broad- side i oh /i ol min storage speed parity comments alight-loado buffer and line driver functions 74f455/456 8-bit inv/ninv 3-st yes 15/64ma none 7.5ns yes multiple/ctr pkg. gnd pins, s e , s o = 15/64ma 74f540/541 8-bit inv/ninv 3-st yes 15/64ma none 7.5ns no broadside pinout of 74f240 74f655a/656a 8-bit inv/ninv 3-st yes 15/64ma none 7.5ns yes s e , s o = 15/64ma 74f827/828 10-bit ninv/inv 3-st yes 15/64ma none 9.0ns no alight-loado register and latch functions 74f821/822 10-bit ninv/inv 3-st yes 15/64ma reg 100mhz no data, mr , oe, & clock en inputs 74f823/824 9-bit ninv/inv 3-st yes 15/64ma reg 100mhz no data, mr , oe, & clock en inputs 74f825/826 8-bit ninv/inv 3-st yes 15/64ma reg 100mhz no data, mr , oe, & clock en inputs 74f841/842 10-bit ninv/inv 3-st yes 15/48ma latch 100mhz no data, mr , oe, & le enable inputs 74f843/844 9-bit ninv/inv 3-st yes 15/48ma latch 100mhz no data, mr , oe, & le enable inputs 74f845/846 8-bit ninv/inv 3-st yes 15/48ma latch 100mhz no data, mr , oe, & le enable inputs alight-loado transceiver functions 74f545 8-bit ninv a n 3-st yes 3/24ma none 7.0ns no b n 3-st yes 15/64ma none 7.0ns no 74f550/551 8-bit ninv/inv b n 3-st yes 15/64ma b n -reg 10.5ns no a n b n , error, status registers, 50mhz a n 3-st yes 3/24ma a n -reg 10.5ns no b n a n , multiple/center pkg. gnd pins ** 74f552 8-bit ninv b n 3-st yes 15/64ma b n -reg 10.5ns yes a n b n , parity, error , status registers a n 3-st yes 3/24ma a n -reg 10.5ns yes b n a n , multiple/center pkg. gnd pins ** 74f588 8-bit ninv a n = 3-st yes 3/24ma none 7.5ns no b n 3-st yes 15/64ma none 7.5ns no ieee-488/gpib w/line term. resistors 74f620/623 8-bit inv/ninv b n 3-st yes 15/64ma none 7.5ns no a n b n a n 3-st yes 3/24ma none 7.5ns no b n a n 74f621/622 8-bit ninv/inv b n oc yes oc/64ma none 13.0ns no a n b n a n oc yes oc/24ma none 12.5ns no b n a n 74f640 8-bit inv a/b 3-st yes 15/64ma none 7.5ns no a n ? b n 74f641/642 8-bit ninv/inv b n oc yes oc/64ma none 13.0ns no a n b n a n oc yes oc/20ma none 12.0ns no b n a n 74f646a/648a 8-bit ninv/inv a/b 3-st yes 15/48ma 2 reg 11.0ns no a n ? b n , registers for a n & b n ports, 80mhz (min.) 74f647/649 8-bit ninv/inv ab oc yes oc/64ma 2 reg 19.5ns no a n ? b n , registers for a n & b n ports, 40mhz (min.) 74f651a/652a 8-bit inv/ninv a/b 3-st yes 15/48ma 2 reg 11.5ns no a n ? b n , registers for a n & b n ports, 80mhz (min.) 74f653/654 8-bit ninv/inv b n 3-st yes 15/64ma b n -reg 11.0ns no a n b n , b n port = 85mhz (min.) a n oc yes oc/64ma a n -reg 20.0ns no b n a n , a n port = 45mhz (min.) 74f657 8-bit ninv b n 3-st yes 15/64ma none 8.0ns yes a n b n , parity, error = 15/64ma a n 3-st yes 3/24ma none 8.0ns no b n a n , multiple/center pkg. gnd pins 74f861/862 10-bit ninv/inv a/b 3-st yes 15/64ma none 10.0ns no a n ? b n 74f863/864 9-bit ninv/inv a/b 3-st yes 15/64ma none 10.0ns no a n ? b n 74f1245 8-bit ninv b n 3-st yes 15/64ma none 8.0ns no a n b n , alight-loado pin-for-pin 'f245 replacement a n 3-st yes 3/24ma none 8.0ns no b n a n 74f2951/2952 8-bit inv/ninv a/b 3-st yes 15/64ma 2 reg 12.5ns no a n ? b n , registers for a n & b n ports, 80mhz (min.) ** notes: all parameters are worst-case, unless otherwise specified. 3-st = 3-state oc = open collector reg = low-to-high edge clocked d-type register latch = high logic level on the latch enable logic, data passes directly through d-type latch, high-to-low logic level transition of the latch enable, data is stored in the d-type latch. ** = these devices utilize standard fast input structures producing input currents of +20 m a and 0.6ma. mr = master reset oe = output enable
philips semiconductors application note an214 74f extended octal-plus family applications yyyy mmm dd 14 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. date of release: 03-98 document order number: 9397 750-05222
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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